[1] B. Yu et al., “Limits of gate oxide scaling in nanotransistors,”
in Proc.Symp. VLSI Technol., pp. 90–
91,2000.
[2] Arulvani, M. ; B.S.Abdhur Rahman Univ. Vandalur,
Chennai, India ; Karthikeyan, S.S. ; Neelima, N.
“Investigation of process variation on register files in
65nm technology” Emerging Trends in VLSI, Embedded
System, Nano Electronics and Telecommunication
System (ICEVENT), 2013 International
Conference,2013.
[3] B.H. Calhoun, Yu Cao, Xin Li, Ken Mai, L.T. Pileggi,
R.A. Rutenbar, K.L. Shepard, “Digital circuit design
challenges and opportunities in the era of nanoscale CMOS”, in: Proceedings of the IEEE, vol. 96, issue 2,
pp. 343–365,feb. 2008.
[4] Seevinck, E., et al.: ‘Static-noise margin analysis of
MOS SRAM cells’,IEEE, J. Solid-State Circuits, SC-22,
(5), pp. 748–754,1987.
[5] Sheng Lin,Yong-BinKim n, FabrizioLombardi “Design
and analysis of a 32 nm PVT tolerant CMOS SRAM cell
for low leakage and high stability” Department of
Electrical and Computer Engineering, Northeastern
University, 360 Huntington Avenue, Boston, MA 02115,
USA, INTEGRATION, the VLSI journal 43 (2010) 176–
187,2010.
[6] Vasudha Gupta and Mohab Anis, Member, IEEE.,
“Statistical Design of the 6T SRAM Bit Cell” IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS—I:
REGULAR PAPERS, VOL. 57, NO. 1, JANUARY
2010.
[7] Kenji Noda, Member, IEEE, Koujirou Matsui, Koichi
Takeda, and Noritsugu Nakamura “A Loadless CMOS
Four-Transistor SRAM Cell in a 180nm Logic
Technology” IEEE TRANSACTIONS ON ELECTRON
DEVICES, VOL. 48, NO. 12, DECEMBER 2001.
[8] Lage, C. ; Adv. Products Res. & Dev. Lab., Motorola
Inc., Austin, TX, USA ; Hayden, J.D. ; Subramanian, C.
“Advanced SRAM technology-the race between 4T and
6T cells” Electron Devices Meeting, 1996. IEDM '96.,
International,dec.1996.
[9] Tseng, Y.H., et al.: ‘A new 7-transistor SRAM cell
design with high read stability’. 2010 Int. Conf. on
Electronic Device, Systems and Applications,
(ICEDSA2010), Kuala Lumpur, Malaysia, pp. 43–
47,2010.
[10] Chang, L., et al.: “An 8T-SRAM for variability tolerance
and low-voltage operation in high-performance caches”,
IEEE J. Solid-State Circuits, 43, (4), pp. 956–962,2008.
[11] L. Chang, D.M. Fried, J. Hergenrother, J.W. Sleight,
R.H. Dennard, R.K. Montoye, L. Sekaric, S.J. McNab,
A.W. Topol, C.D. Adams, K.W. Guarini, W. Haensch,
Stable SRAM cell design for the 32 nm node and
beyond, in: Proceedings of the 2005 Symposium on VLSI
Technology, Digest of Technical Papers, pp. 128–
129,june 2005.
[12] Chang, I.J., et al.: ‘A 32kb 10T sub-threshold SRAM
array with bit- interleaving and differential read scheme
in 90nm CMOS’, IEEE J. Solid-State Circuits, 44, (2),
pp. 650–658,2009.