A Modified 8-Transistor SRAM Cell Design with High Stability and Low Power Applications  
  Authors : Amritpal Singh Gill; Chakshu Goel

 

SRAM occupies two-third area of VLSI chips, therefore it dominates the total power consumption. To enhance the performance of these chips, SRAM cell should meet the requirement of lesser power consumption. This paper presents a new 8T SRAM cell that is efficient in Dynamic power consumption in Write mode and Leakage power consumption when compared with referred 9T SRAM cell and standard 6T SRAM cell. The design is simulated in 45-nm CMOS technology that results 18.6% reduction in Dynamic power consumption during Write mode and 28.4 % reduction in Leakage power consumption as compared to referred 9T SRAM cell. When compared with standard 6T SRAM cell this new 8T SRAM cell results 20.1 % reduction in Dynamic power consumption during Write mode and 18.1 % reduction in Leakage power consumption.

 

Published In : IJCAT Journal Volume 1, Issue 6

Date of Publication : 31 July 2014

Pages : 222 - 226

Figures : 05

Tables : 01

Publication Link : A Modified 8-Transistor SRAM Cell Design with High Stability and Low Power Applications

 

 

 

Amritpal Singh Gill : ECE Department, Shaheed Bhagat Singh State

Chakshu Goel : ECE Department, Shaheed Bhagat Singh State

 

 

 

 

 

 

 

Static Random Access Memory (SRAM)

Static Noise Margin (SNM)

CMOS

In this paper, 8T SRAM cell is proposed in which a way of accessing the cell during the write operation is changed and also the discharging level of bit-line is increased to 2/3 VDD. Due to this, it is found that the Leakage power consumed by this proposed 8T SRAM cell is reduced by 28.4 % and 18.1% when compared to referred 9T SRAM cell and standard 6T SRAM cell respectively. The Dynamic power consumption in write mode of proposed 8T SRAM cell is also reduced by 18.6 % and 20.1% when compared with referred 9T SRAM cell and standard 6T SRAM cell respectively. Further work can be done to analyze the write speed and area consumption of proposed 8T SRAM cell.

 

 

 

 

 

 

 

 

 

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