Carry Select Adder (CSLA) is one of the
fastest adders used in many data-processing processors to
perform fast arithmetic functions. From the structure of the
CSLA, it is clear that there is scope for reducing the area and
power consumption in the CSLA. This work uses a simple
and efficient gate-level modification to significantly reduce
the area and power of the CSLA. Based on this
modification 8-, 16-, 32-, and 64-b square-root CSLA
(SQRT CSLA) architecture have been developed and compared
with the regular SQRT CSLA architecture. The proposed
design has reduced area and power as compared with the
regular SQRT CSLA with only a slight increase in the delay.
This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand
with logical effort and through custom design and layout
in 0.18-m CMOS process technology. The results analysis
shows that the proposed CSLA structure is better than the
regular SQRT CSLA.
Published In : IJCAT Journal Volume 2, Issue 1
Date of Publication : 31 January 2015
Pages : 01 - 04
Figures :04
Tables : 01
Publication Link :Carry Select Adder Low Power and Area-Efficient
G. Swarna Manjari : Dept of ECE, Avanthi Inst. Of Engg. Tech,
Bhogapuram, Vizianagaram,Andhra Pradesh, India
Sateesh Kumar Potnuru : Dept of ECE, Avanthi Inst. Of Engg. Tech,
Bhogapuram, Vizianagaram, Andhra Pradesh, India
Application-specific integrated circuit (ASIC)
area efficient
CSLA
low power
A simple approach is proposed in this paper to reduce the
area and power of SQRT CSLA architecture. The reduced
number of gates of this work offers the great advantage in
the reduction of area and also the total power. The
compared results show that the modified SQRT CSLA has
a slightly larger delay (only 3.76%), but the area and
power of the 64-b modified SQRT CSLA are significantly
reduced by 17.4% and 15.4% respectively.
[1] O. J. Bedrij, “Carry-select adder,” IRE Trans.
Electron. Comput., pp. 340–344, 1962.
[2] B. Ramkumar, H.M. Kittur, and P. M. Kannan, “ASIC
implementation of modified faster carry save adder,”
Eur. J. Sci. Res., vol. 42, no. 1, pp. 53–58, 2010.
[3] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder
using single ripple carry adder,” Electron. Lett., vol.
34, no. 22, pp. 2101–2103, Oct. 1998.
[4] Y. Kim and L.-S. Kim, “64-bit carry-select adder with
reduced area,” Electron. Lett., vol. 37, no. 10, pp.
614–615, May 2001.
[5] J. M. Rabaey, Digtal Integrated Circuits—A Design
Perspective. Upper Saddle River, NJ: Prentice-Hall,
2001.
[6] Y. He, C. H. Chang, and J. Gu, “An area efficient 64-
bit square root carry-select adder for lowpower
applications,” in Proc. IEEE Int. Symp. Circuits Syst.,
2005, vol. 4, pp. 4082–4085.
