Processors are generally able to perform operations
on operands faster than the access time of large capacity main
memory. Though semiconductor memory which can operate at
speeds comparable with the operation of the processor exists, it
is not economical to provide all the main memory with very high
speed semiconductor memory. The problem can be alleviated by
introducing a small block of high speed memory called a cache
between the main memory and the processor. This paper aims to
design and implement the cache memory, using the PIC
microcontroller. It is designed to give students the ability to
monitor cache systems behavior and determine the various cache
systems performance. Cache designing system must be able to
show the following results:
• Number of hits: Which are referred to the number of times and
indicate that the data were found in the cache.
•Number of misses: which are referred to the number of times
and indicate that the data were not found in the cache.
• Hit ratio: Which is equaling (number of hits/ (number of hits+
number of misses)).
Published In : IJCAT Journal Volume 2, Issue 1
Date of Publication : 31 January 2015
Pages : 05 - 11
Tables : --
Publication Link :Designing a Cache Memory Simulator Using Pic
Mozamel M. Saeed : Dept. of Computer Science, Salman Bin Abdul-Al Aziz University ,Aflaj, Saudi Arabia
Hamza S. Alsiah : Dept. of Computer Engineering, Al-Hussein Bin Talal University ,Amman, Jordan
Doaa S. Alsiah : Dept. of Computer Science, Salman Bin Abdul-Al Aziz University Aflaj, Saudi Arabia
In the proposed method, we have built small design of
Cache memory and RAM by viewing, storing, inter, and
how to search data in Cache memory; Searching and
viewing data of RAM. However, cache memory simulator
processes in this design how to store and address the data
for watching content and techniques of working cache
memory clearly and simply. The proposed methods have
been implemented by MIKROBASIC.
 An-Najah national university, faculty of engineering,
cache simulator project, 2013.
 Udayan VBapat, M.S.research - computer engineering,
north Carolina state university,2011.