Electrocardiogram (ECG) is the physical
construal of the electrical behavior created by the heart
muscles. The ECG signal consists of low amplitude voltage
in the presence of high amplitude offset and noise. A new
power-efficient electrocardiogram acquisition system uses
a fully digital architecture to reduce the power
consumption and delay time. This digital architecture is
capable of operating with a low supply voltage of 0.3 V. In
this architecture analog blocks such as low-noise amplifier
(LNA) and filters are not used. A digital feedback loop is
engaged to cancel the impact of the dc offset on the circuit,
which eliminates the need of coupling capacitors. The
circuit is implemented in 65nm CMOS process. The
simulation results show that the front-end circuit of digital
architecture consumes 0.22nW of power.
Published In:IJCAT Journal Volume 3, Issue 11
Date of Publication : November 2016
Pages : 477-482
Figures :07
Tables : --
R. Sivaranjani : PG student, Department of ECE
Vivekanandha College of engineering for women, Tiruchengode.
Dr. D. Sasikala : Head/ECE, Department of ECE
Vivekanandha College of engineering for women, Tiruchengode.
In the expectation of the future dominance of digital
CMOS technology, a fully digital front-end architecture
for an ECG acquisition system was designed. In this
system, active electrode, DCC and switching circuits were implemented. The system has low power
consumption, reduced delay time and less complexity.
This digital architecture is simulated in 65nm CMOS
technology at 0.3 V supply voltage. The simulated
power consumption is 0.22nW their corresponding delay
is -1.3071e-007.In future, digital architecture can be
modified to accept an offset voltage larger than ±300
mV. In order to do this, the resolution of the DCC circuit
and demultiplexer should be increased to 8 bits. A
moving average mechanism embedded into the VTC of
the front end eliminates the need for anti-aliasing filter.
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