The rapid growths of portable electronic
devices are increased and they are designing with low
power and high speed is critical. To design a three input
XOR and XNOR gates using the systematic cell design
methodology can be achieved by implementing
transmission gate. By this type of designing the low power
and high speed can achieved. This architecture is used to
maintain summation results for after completing addition
process. To reduce the overall leakage power level and size
of the circuit, this simulation is carried out using TSMC
90nm in Tanner EDA Tool.
Published In:IJCAT Journal Volume 3, Issue 11
Date of Publication : November 2016
Pages : 487-492
Figures :05
Tables : 01
G. Nagasundari : PG student, Department of ECE,
Vivekanandha College of engineering for women, Tiruchengode.
S.R. Prabakar : AP/ECE, Department of ECE
Vivekanandha College of engineering for women, Tiruchengode.
To design a three input XOR/XNOR gate and the
analytical expression of optimum frequency and supply
voltage under minimum energy condition has been
verified through simulation in 90-nm technology. The
performance of the proposed circuits can operate at lowvoltages,
and have good output levels. According to the
simulation results, the proposed circuit offers a better
result and more competitive than other design. It offers
the lowest power dissipation at a low supply voltage. It
has a good driving capability with good output
signal in all input combinations and well
performance especially in low supply voltage
compared to the previous designs. Thus, the proposed
circuit is suitable for low-voltage and low-power
application.In future work 8-bit adder architecture based
on the design of three-input XOR/XNOR gate will be
designed. The power consumption and delay
performance are calculated and compared with the
existing system.
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