The paper presents a low Power consumption
plays an important role in the present day VLSI technology.
Power consumption of an electronic device can be reduced by
adopting different design styles. Multipliers play a major role
in high performance systems. This project focuses on a novel
energy efficient technique called adiabatic logic which is
based on energy recovery principle and power is compared
by designing a multiplier. CMOS technology plays a
dominant role in designing low power consuming devices,
compared to different logic family CMOS has less power
dissipation. Adiabatic logic style is assumed to be an
attractive solution for low power electronic applications. By
using Adiabatic techniques energy dissipation in PMOS
network can be minimized and various of energy stored at
load capacitance can be recycled instead of dissipated as heat.
Tanner EDA tools are used for simulation.
Published In:IJCAT Journal Volume 3, Issue 11
Date of Publication : November 2016
Pages : 498-503
Figures :08
Tables : --
G. Nathiya : PG student, Department of ECE,
Vivekanandha College of engineering for women, Tiruchengode.
M. Balasubaramani : AP/ /ECE student, Department of ECE
Vivekanandha College of engineering for women, Tiruchengode.
In future, a multiplier and And gate is designed based on
the adiabatic logic methods using CMOS technology. The
multiplier consists of full adder, And gate and half adder.
Here a full adder and half adder is designed using
Tanner. The proposed system is simulated in 32nm CMOS
technology at supply voltage of 1.6V. The delay can be
reduced .
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