Designing of High-Performance Carry Select Adder Using CMOS Technology

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This paper presents a novel designing approach for high performance carry select adder(CSLA). As the demand for the portable equipment’s like mobile phones and laptops increases in our day to day life. So, greater attention has to been focused in designing of processors that has less power consumption, low cost and have a better performance. Adders are the main building block of processors. The performance of the adder greatly influence the performance of the processors. To perform fast addition operation at a lower cost, carry select adder is most suitable among other adders. The carry select adder (CSLA) consists of full adders (FAs) and multiplexers. The proposed structure is assessed by the power consumption of the full adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that full adder has low power consumption.

Published In : IJCAT Journal Volume 3, Issue 11

Date of Publication : November 2016

Pages : 493-497

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Neethumol. A. : PG student, Department of ECE, Vivekanandha College of engineering for women, Tiruchengode.

S. Gnanamurugan : AP/ECE, Department of ECE Vivekanandha College of engineering for women, Tiruchengode.

CSLA, FAs, & CMOS Technology

In future, a carry select adder is designed based on the concatenation and incrementation methods using static CMOS technology. The carry select adder consists of full adders and multiplexers. Here a full adder and multiplexer is designed using Tanner. The proposed system is simulated in 32nm CMOS technology at supply voltage of 1.2V. The power consumption of the full adder is 2.7µW.

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