As the CMOS technology is scaling down to the
nanometer regime, process variations have been increased. In
particular, the increase of delay variations has seriously
affected the design periods and timing yields. To estimate
more accurately these delay variations, statistical static
timing analysis (SSTA), which considers delay variations
statistically, has been proposed. The MOS transistor is the
basic building block of integrated circuits. Scaling of the
MOS transistor improves its size, cost and performance.
Today’s fabricated integrated circuits are many times faster
and occupy much less area, like today’s microprocessors that
contain nearly one billion transistors on a single chip. In such
designs, it is important to the timing yield at the design phase
because, at this phase, we can consider the trade-offs between
chip performance and yield.
Published In:IJCAT Journal Volume 3, Issue 11
Date of Publication : November 2016
Pages : 466-471
Figures :08
Tables : --
R. S. Halke : Dr. DYPSOET, Lohgaon, Pune, 412105.
Bhushan Malkapurkar : Dr. DYPSOET, Lohgaon, Pune, 412105.
SSTA, Scaling, variations
Statistical Static Timing Analysis is better analysis than
the traditional Static Timing Analysis. It is seen that the
proposed method is easy to determine the propagation
delay for the complex digital circuits.
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