There are different parameters need to be focused
while designing a VLSI circuit. Some of them are power, area,
and speed. Hence these can be referred as challenging problems.
Out of these, power dissipation is a critical parameter in modern
VLSI design field. Multiplication occurs frequently in finite
impulse response (FIR) filters, fast Fourier transforms, discrete
cosine transforms, convolution, and to save significant power
consumption of a VLSI design, it is a good direction to reduce
its dynamic power that is the major part of total power
dissipation. This paper summarizes and examines techniques
which are involved in multipliers. It broadly covers Booth
multipliers, Wallace tree multipliers and Distributed arithmetic
Published In : IJCAT Journal Volume 1, Issue 6
Date of Publication : 31 July 2014
Pages : 278 - 283
Tables : 02
Publication Link : A Survey on Power Reduction Techniques in FIR Filter
Pooja Madhumatke : has done B. Tech from S.N.D.T University,
Mumbai in Electronics and Communication. Currently she is a final
year (M.E. student) pursuing her post graduation in the field of
Embedded System & Computing from Nagpur University. She has
published papers in International Conference and attended an
International Conference held in year 2014. Currently she is working
for her final year project in the same field of filters.
Shubhangi Borkar : has done Engineering from Nagpur
University in Computer Science and Technology. She has also
completed her post graduation from Nagpur University. Currently she
is working as Assistant Professor in NIT, Nagpur University. She has
published several papers in International and National conferences.
Dinesh Katole : has done Engineering from Nagpur University
in Electronics and Telecommunication. He has also completed his
post graduation from Nagpur University. Currently he is working as Assistant Professor in NIT, Nagpur University. He has published
several papers in International and National conferences. He is also
continuing his P.hd program.
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